• The first chapter presents a summary of the fundamentals of digital design to refresh readers' knowledge and prepare them for the rest of the book.
• A wide range of important digital design concepts, including Algorithmic State Machine (ASM) charts, micro-programming, one-hot design, design for synthesis, testing, etc., are covered.
• Many digital system design examples, ranging in complexity from a simple binary adder to a microprocessor, help readers learn design skills.
• Steps in the design flow are clearly illustrated and explained.
• Two chapters (Chapters 3 and 6) treat the basics of all programmable logic devices and provide details of synthesis, mapping, and routing to FPGAs.
• Materials are presented generically, rather than attached to a specific vendor or product family.
• The authors help students develop the design skill of putting together bigger designs from smaller pieces.
• A unique chapter on testing presents information on Built In Self-Test (BIST), Boundary Scan testing, and LFSRs.
• Includes Mindtap which is an interactive, customizable and complete learning solution. It includes a MindTap Reader and a library of learning apps (e.g., CNOW, Aplia, ReadSpeaker, Merriam-Webster dictionary, MyContent, RSS Feed, Kaltura, Progress app, etc.).

1. REVIEW OF LOGIC DESIGN FUNDAMENTALS.

Combinational Logic. Boolean Algebra and Algebraic Simplification. Karnaugh Maps. Designing with NAND and NOR Gates. Hazards in Combinational Circuits. Flip-Flops and Latches. Mealy Sequential Circuit Design. Design of a Moore Sequential Circuit. Equivalent States and Reduction of State Tables. Sequential Circuit Timing. Tristate Logic and Busses.

2. INTRODUCTION TO VERILOG.

Computer-Aided Design. Hardware Description Languages. Verilog Description of Combinational Circuits. Verilog Modules. Verilog Assignments. Procedural Assignments. Modeling Flip-Flops Using Always Block. Always Blocks Using Event Control Statements. Delays in Verilog. Compilation, Simulation, and Synthesis of Verilog Code. Verilog Data Types and Operators. Simple Synthesis Examples. Verilog Models for Multiplexers. Modeling Registers and Counters Using Verilog Always Statements. Behavioral and Structural Verilog. Constants. Arrays. Loops in Verilog. Testing Verilog Model. A Few Things to Remember.

3. INTRODUCTION TO PROGRAMMABLE LOGIC DEVICES.

Brief Overview of Programmable Logic Devices. Simple Programmable Logic Devices (SPLDs). Complex Programmable Logic Devices (CPLDs). Field-Programmable Gate Arrays (FPGAs).

4. DESIGN EXAMPLES.

BCD to 7-Segment Display Decoder. A BCD Adder. 32-Bit Adders. Traffic Light Controller. State Graphs for Control Circuits. Scoreboard and Controller. Synchronization and Debouncing. A Shift-and-Add Multiplier. Array Multiplier. A Signed Integer/Fraction Multiplier. Keypad Scanner. Binary Dividers.

5. SM CHARTS AND MIRCOPROGRAMMING.

State Machine Charts. Derivation of SM Charts. Realization of SM Charts. Implementation of the Dice Game. Microprogramming. Linked State Machines.

6. DESIGNING WITH FIELD PROGRAMMABLE GATE ARRAYS.

Implementing Functions in FPGAs. Implementing Functions Using Shannon''s Decomposition. Carry Chains in FPGAs. Cascade Chains in FPGAs. Examples of Logic Blocks in Commercial FPGAs. Dedicated Memory in FPGAs. Dedicated Multipliers in FPGAs. Cost of Programmability. FPGAs and One-Hot State Assignment. FPGA Capacity: Maximum Gates versus Usable Gates. Design Translation (Synthesis). Mapping, Placement, and Routing.

7. FLOATING-POINT ARITHMETIC.

Representation of Floating-Point Numbers. Floating-Point Multiplication. Floating-Point Addition. Other Floating-Point Operations.

8. ADDITIONAL TOPICS IN VERILOG.

Verilog Functions. Verilog Tasks. Multi-Valued Logic and Signal Resolution. Built-in Primitives. User Defined Primitives. SRAM Model. Model for SRAM Read/Write System. Rise and Fall Delays of Gates. Named Association. Generate Statements. System Functions. Compiler Directives. File I/O Functions. Timing Check.

9. DESIGN OF A RISC MICROPROCESSOR.

The RISC Philosophy. The MIPS ISA. MIPS Instruction Encoding. Implementation of a MIPS Subset. VHDL Model.

10. HARDWARE TESTING AND DESIGN FOR TESTABILITY.

Testing Combinational Logic. Testing Sequential Logic. Scan Testing. Boundary Scan. Built-In Self-Test.

Charles Roth, University of Texas, Austin

Charles Roth is Professor Emeritus in Electrical and Computer Engineering at the University of Texas at Austin, where he taught Digital Design for more than four decades. He is the author of Fundamentals of Logic Design, which is in its sixth edition, and Digital Systems Design using VHDL, which is in its second edition.

Lizy Kurian John, University of Texas, Austin

Lizy John is the B. N. Gafford Professor in Electrical and Computer Engineering at the University of Texas at Austin. Dr. John has been teaching and conducting research in computer architecture and digital systems design for almost two decades. She has coauthored DIGITAL SYSTEMS DESIGN USING VHDL and DIGITAL SYSTEMS DESIGN USING VERILOG and has edited several successful books on computer performance evaluation and workload characterization. She is an IEEE Fellow.

Byeong Kil Lee, University of Texas, San Antonio

Byeong Kil Lee is Assistant Professor in Electrical and Computer Engineering at the University of Texas at San Antonio, teaching digital design and computer architecture. Before joining academia two years ago, he worked for Texas Instruments for five years. He has several years of industry Verilog design experience.